The present invention relates to logic circuit design, and more particularly, to technology of top-down design from C language description.
Conventionally, hardware of a logic circuit has been designed with a hardware description language (HDL) such as Verilog-HDL and VHDL. In recent years, with the advent of system level description languages called SpecC and SystemC, hardware design with a C language has become a focus of attention.
One of prior art techniques provides a language with which simulation can be performed at an intermediate level between algorithm description and register transfer (RT) level description (disclosed in Japanese Laid-Open Patent Publication No. 2001-109788). FIG. 16 illustrates a conventional logic simulation system, in which an algorithm description 103 is degraded to clock level description. A plurality of functions of the algorithm description 103 are disassembled into partial functions operable in a unit clock, and the partial functions are assembled to enable the plural functions to operate. The plurality of functions are expressed in a language using a register as a variable, in the form of a clock level simulator 108 that is a clock level description.
As shown in FIG. 16, a clock level verification section 106 is provided between an algorithm verification section 102 and a RT level verification section 116. The clock level verification section 106 includes a clock level system 107, which includes the clock level simulation model 108 as the clock level description and a clock level CPU model 109. The clock level system 107 is automatically generated by a build-in C compiler 111, and the description thereof is converted using a register, a tool provided by a general-use function synthesis tool 112, as a term (a word or a linear variable). The algorithm description 103 is converted into the clock level simulation model 108 with a model conversion tool 113 having a tool described in the function synthesis tool 112. The clock level CPU model 109 is automatically generated from a C program 104 by the build-in C compiler 111. A clock base simulator 114 is formed of the clock level simulation model 108 and the clock level CPU model 109.
The prior art technique has the following problems. In recent years, operation synthesis tools and the like enabling direct conversion into RT level description in HDL have become available. However, circuits designed with such tools are not only significantly large in scale but also low in quality, compared with circuits directly designed with RT level description. In addition, since free control of the circuit configuration is not allowed for circuits designed with the above tools, it is very difficult to obtain a circuit intended by the designer, and also very difficult to read a designed circuit.
In the prior art technique described above, a model is generated considering all of three main hardware components, namely, the data path, the control and the clock. Therefore, the logic verification using the clock level simulator remains complicated although the speed of the verification is faster than RT level verification. In addition, due to the disassembly into functions processible in clock units, the level of abstraction of the resultant description is degraded, resulting in a description as low as the RT level. Therefore, the prior art technique fails to solve the problems relating to the RT level design, such as difficulty in response to change of specifications and complexity in examination of hardware architecture. This still requires detailed design and examination as those required in the RT level design.
To state more specifically, the description is hardware-oriented to enable clock-unit operation. For example, the clock level verification includes not only the clock but also reset. Although the reset is required to determine the initial state of hardware, it is not required at the stage of examination of hardware architecture and verification of functions. It is rather important to clarify basics of hardware such as the unit of processing, the function block and the unit of control.
The examination of hardware architecture and design/verification of hardware functions considering clock operation are equivalent to examining three functions of computation function, control function and timing function simultaneously. This complicates the concept. In other words, the clock and the reset are unnecessary during the examination of hardware architecture and the design of hardware functions, and rather cause complexity of the examination. This fails to make use of the advantage of the design in a C language providing a high level of abstraction.
In the prior art technique described above, to obtain the clock level simulation model 108, it is necessary to write detailed control description by disassembling processing in clock units with a control data flow graph (CDFG) or the like. In this situation, design will be considerably difficult without visualization of hardware in cycle operation.
In the description of the clock level simulation model 108, one “case” sentence corresponds to one clock, and the relevant function is broken for each “case” to simulate a clock. Therefore, to terminate processing for the function, the function must be called repeatedly every cycle. This will be a major cause of reduction in simulation speed. Moreover, one state transition must be allocated to one function.